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march 2010 doc id 16857 rev 2 1/25 25 LNBH24L dual lnbs supply and control ic with step-up and i2c interface features complete interface between lnbs and i2c bus built-in dc-dc converter for single 12 v supply operation and high efficiency (typ. 93%@0.5 a) selectable output current limit by external resistor compliant with main sate llite receivers output voltage specification auxiliary modulation in put (extm) facilitates diseqc? 1.x encoding low-drop post regulator and high efficiency step-up pwm with integrated power n-mos allow low power losses overload and over-temperature internal protections with i2c diagnostic bits output voltage and output current level diagnostic feedback by i2c bits lnb short circuit dynamic protection +/- 4 kv esd tolerant on output power pins description intended for analog and digital dual satellite receivers/sat-tv, sat-pc cards, the LNBH24L is a monolithic voltage regulator and interface ic, assembled in qfn 5x5 epad, specifically designed to provide the 13 / 18 v power supply and the 22 khz tone signaling for two independent lnb down-converters in the antenna dishes and/or multi-switch box. in this application field, it offers a dual tuner stbs complete solution with extremely low component count, low power dissipation together with simple design and i2c standard interfacing. qfn32 5 x 5 mm (epad) table 1. device summary order code package packaging LNBH24Lqtr qfn32 5 x 5 (exposed pad) tape and reel www.st.com
contents LNBH24L 2/25 doc id 16857 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 application information (valid for each section a/b) . . . . . . . . . . . . . . . . . . 5 2.2 diseqc? data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 diseqc? 1.x implementation by extm pin . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 diseqc? 1.x implementation with votx and extm pin connection . . . . 5 2.5 pdc optional circuit for diseqc? 1.x applications using votx signal on to extm pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 7 2.10 thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.11 output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 lnbh24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 system register (sr, 1 byte for each section a and b) . . . . . . . . . . . . . . 15 7.3 transmitted data (i2c bus write mode) for each sections a/b . . . . . . . . . 15
LNBH24L contents doc id 16857 rev 2 3/25 7.4 diagnostic received data (i2c read mode) for both sections a/b . . . . . . . 16 7.5 power-on i2c interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 address pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 diseqc? implementation for each section a/b . . . . . . . . . . . . . . . . . . . 17 8 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
block diagram LNBH24L 4/25 doc id 16857 rev 2 1 block diagram figure 1. block diagram sda scl LNBH24L addr- a a-gnd i2c diagnostics i2c interface dsqin- a vup - a vorx - a pdc - a votx- a lx- a 22 khz oscillator pwm controller rsense en- a vsel- a linear post-reg +protections +diagnostics ttx- a en- a vsel- a vout- a control extm- a dsqin- b vup - b vorx- b pdc - b votx- b lx- b pwm controller rsense en- b vsel- b linear post-reg +protections +diagnostics ttx- b en- b vsel- b vout- b control extm- b p-gnd- a p-gnd- b addr- b byp vcc preregulator +u.v.lockout +p.on reset vcc - l isel- a isel- a isel- b isel- b ttx- a ttx- b ten- a ten- b ten- b ttx- a ttx- b ten- a fb fb pull down controller pull down controller 22 khz oscillator - - 2 i - - - - - - - - - - - - - - - - - rsense - - - - - - - - - - - - - - b ten- b fb fb fb fb sda scl LNBH24L addr- a a-gnd i2c diagnostics i2c interface dsqin- a vup - a vorx - a pdc - a votx- a lx- a 22 khz oscillator pwm controller rsense en- a vsel- a linear post-reg +protections +diagnostics ttx- a en- a vsel- a vout- a control extm- a dsqin- b vup - b vorx- b pdc - b votx- b lx- b pwm controller rsense en- b vsel- b linear post-reg +protections +diagnostics ttx- b en- b vsel- b vout- b control extm- b p-gnd- a p-gnd- b addr- b byp vcc preregulator +u.v.lockout +p.on reset vcc - l isel- a isel- a isel- b isel- b ttx- a ttx- b ten- a ten- b ten- b ttx- a ttx- b ten- a fb fb pull down controller pull down controller 22 khz oscillator - - 2 i - - - - - - - - - - - - - - - - - rsense - - - - - - - - - - - - - - b ten- b fb fb fb fb
LNBH24L introduction doc id 16857 rev 2 5/25 2 introduction the LNBH24L includes two completely independent sections. unless for the v cc and i2c inputs, each circuit can be separately controlled and have its independent external components. all the below specification must be considered equal for both sections (a/b). 2.1 application information (valid for each section a/b) this ic has a built-in dc-dc step-up converter that, from a single source from 8 v to 15 v, generates the voltages (v up ) that let the linear post-regulator to work at a minimum dissipated power of 0.55 w typ. @ 500 ma load per channel (the linear post-regulator drop voltage is internally kept at v up - v out = 1.1 v typ.). an under voltage lockout circuit will disable the whole circuit when the supplied v cc drops below a fixed threshold (6.7 v typically). note: in this document the v out is intended as the voltage present at the linear post-regulator output (v orx pin). 2.2 diseqc? data encoding the new internal 22 khz tone generator is factory trimmed in accordance to the standards, and can be selected by i2c interface ttx bit (or ttx pin) and activated by a dedicated pin (dsqin) that allows immediate diseqc? data encoding, or through ten i2c bit in case the 22 khz presence is requested in continuous mode. in stand-by condition (en bit low) the ttx function must be disabled setting ttx to low. 2.3 diseqc? 1.x implementation by extm pin in order to improve design fl exibility and reduce the total a pplication cost, an analogic modulation input pin is available (extm) to generate the 22 khz tone superimposed to the v orx dc output voltage. an appropriate dc blocking capacitor must be used to couple the modulating signal source to the extm pin. if the extm solution is used the output r-l filter can be removed (see section 5: application circuits ) saving the external components cost.the pin extm modulates the v orx voltage through the series decoupling capacitor, so that: where v orx (ac) and v extm (ac) are, respectively, the peak to peak voltage on the v orx and extm pins while g extm is the voltage gain from extm to v orx . 2.4 diseqc? 1.x implementation with v otx and extm pin connection if an external 22 khz tone source is not available, it is possible to use the internal 22 khz tone generator signal available through the v otx pin to drive the extm pin. by this way the extm ) ac ( extm ) ac ( orx g v v =
introduction LNBH24L 6/25 doc id 16857 rev 2 v otx 22 khz signal will be superimposed to the v orx dc voltage to generate the lnb output 22 khz tone (see figure 3: LNBH24L with internal tone for diseqc 1.x applications ). the internal 22 khz tone generator available through the v otx pin must be activated during the 22 khz transmission by dsqin pin or by the ten bit.the dsqin internal circuit activates the 22 khz tone on the v otx output with 0.5 cycles 25 s delay from the ttl signal presence on the dsqin pin, and it stops with 1 cycles 25 s delay after the ttl signal is expired. the v otx pin internal circuit must be preventively set on by the ttx function. this can be controlled both through the ttx pin and by i2c bit. as soon as the tone transmission is expired, the v otx must be disabled by setting the ttx to low. the 13 / 18 v power supply is always provided to the lnb from the v orx pin. 2.5 pdc optional circuit for diseqc? 1.x applications using v otx signal on to extm pin in some applications, at light output current (< 50 ma) and in case of heavy output capacitive load, the 22 khz tone can be distorte d. in this case it is possible to add the "optional" external components shown in the typical application circuit (see figure 4: diseqc 1.x using external 22 khz tone generator source through extm pin ) connected between v orx and pdc pin. this optional circuit acts as an active pull-down discharging the output capacitance only when the internal 22 khz tone is activated. 2.6 i2c interface the main functions of the ic are controlled via i2c bus by writing 6 bits on the system register (sr 8 bits in write mode). on the same register there are 5 bits that can be read back (sr 8 bits in read mode) to provide the diagnostic flags of two internal monitoring functions (otf, olf) and three output voltage regist er status (en, vsel, llc) received by the ic (see section 2.8: diagnostic and protection functions ). in read mode there are 3 test bits (test1-2-3) that must be disregarded from the mcu. while, in write mode, there 2 test bits (test4-5) that must be always set low. each section (a/b) has two selectable i2c addresses selectable respectively, by the addr-a and addr-b pins (see ta bl e 1 1 : address pins characteristics ). 2.7 output voltage selection when the ic sections are in stand-by mode (en bit low), the power blocks are disabled. when the regulator blocks are active (en bit hi gh), the output can be logic controlled to be 13 or 18 v by mean of the vsel bit (voltage select) for remote controlling of non-diseqc lnbs. additionally, the LNBH24L is provided with the llc i2c bit that increase the selected voltage value to compensate possible voltage drop along the output line. in stand-by condition (en bit low) all the i2c bits and t he ttx pin must be set low (if the ttx pin is not used it can be left floating but the ttx bit must be set low during the stand-by condition). 2.8 diagnostic and protection functions the LNBH24L has two diagnostic in ternal functions provided via i2c bus by reading 2 bits on the system register (sr bits in read mode). the diagnostic bits are, in normal operation (no
LNBH24L introduction doc id 16857 rev 2 7/25 failure detected), set to low. the diagnostic bits are dedicated to the over-temperature and over-load protections status (otf and olf). 2.9 over-current and short circuit protection and diagnostic in order to reduce the total power dissipation during an overload or a short circuit condition, the device is provided with a dynamic short circuit protection. it is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the pcl bit of the i2c sr. when the pcl (pulsed current limiting) bit is set lo low, the over current protection circuit works dynamically: as soon as an overload is detected, the output is shut- down for a time t off , typically 900 ms. simultaneously the diagnostic olf i2c bit of the system register is set to "1". after this time has elapsed, the output is resumed for a time t on = 1/10 t off = 90 ms (typ.). at the end of t on , if the overload is still detected, the protection circuit will cycle again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low. typical t on + t off time is 990 ms and an internal timer determines it. this dynamic operation can greatly reduce the power dissipat ion in short circuit c ondition, still ensuring excellent power-on start-up in most conditions. however, there could be some cases in which a highly capacitive load on the output ma y cause a difficult start-up when the dynamic protection is chosen. this can be solved by initiating any power start-up in static mode (pcl=1) and, then, switching to the dynamic mode (pcl=0) after a chosen amount of time depending on the output capacitance. when in static mode, the diagnostic olf bit goes to "1" when the current clamp limit is reached and returns low when the overload condition is cleared. 2.10 thermal protection and diagnostic the LNBH24L is also protected against ov erheating: when the junction temperature exceeds 150c (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic otf sr bit is set to "1". normal op eration is resumed and the otf bit is reset to low when the junction is cooled down to 135c (typ.) 2.11 output current limit selection the linear regulator current limit threshold can be set by an external resistor connected to isel pin. the resistor value defines the output current limit by the equation: equation 1 where r sel is the resistor connected between i sel and gnd (see r2 in the typical application circuit). the highest selectable current limit threshold is 0.9 a typ. with r sel = 11 k . the above equation defines the typical thres hold value for each output. however, it is suggestible to not exceed for a long period a total amount of current of 1 a from both sections (i out_a + i out_b < 1 a) in order to avoid the over temperature protection triggering. note: external components are needed to comply to bidirectional diseqc? bus hardware requirements. full compliance of the whole app lication with diseqc? specifications is not implied by the bare use of this ic. notice: diseqc? is a trademark of eutelsat. r sel [a] i max 10000 = r sel [a] i max 10000 =
pin configuration LNBH24L 8/25 doc id 16857 rev 2 3 pin configuration figure 2. pin connections (bottom view) table 2. pin description pin n (sec. a/b) symbol name pin function 21 v cc supply input 8 to 15 v ic dc-dc power supply. 20 v cc? l supply input 8 to 15 v analog power supply. 5 / 2 lx-a / lx-b n-mos drain integrated n-channel power mosfets drain. 16 / 25 v up -a / v up -b step-up voltage input of the linear post-regulators . the voltage on these pins is monitored by the internal step-up controllers to keep a minimum dropout across the linear pass transistors. 18 / 23 v orx -a / v orx -b ldo output port outputs of the integrated low drop linear regulators. see ta bl e 7 for voltage selections and description. 17 / 24 v otx ? a / v otx ? b output port during 22khz tone tx tone outputs to the lnb. see ta bl e 7 for selection. 6 sda serial data bidirectiona l data from / to i2c bus. 7 scl serial clock clock from i2c bus. 10 / 31 dsqin-a / dsqin-b diseqc inputs these pins will accept the diseqc code from the main microcontroller. the LNBH24L will uses this code to modulate the internally generated 22 khz carrier. set to ground if not used. 12 / 29 ttx-a / ttx-b ttx enable these pins can be used, as well as the ttx i2c bits of the system register, to control the ttx function enable before to start the 22 khz tone transmission. set floating or to gnd if not used. 11 / 30 reserved reserved to be connected to gnd. 9 / 32 pdc ? a / pdc ? b pull down control to be connected to the external npn transistors base to reduce the 22 khz tone distorti on in case of heavy capacitive load at light output current. if not used they can be left floating.
LNBH24L pin configuration doc id 16857 rev 2 9/25 pin n (sec. a/b) symbol name pin function 13 / 28 extm-a / extm-b external modulation external modulation inputs act on v orx linear regulator outputs to superimpose an external 22 khz signal. need dc decoupling to the ac source. if not used they can be left floating. 4 / 3 p-gnd-a / p-gnd-b power grounds dc-dc converters power grounds. epad epad exposed pad to be connected with power grounds and to the ground layer through vias to dissipate the heat. 22 a-gnd analog grounds analog circuits grounds. 19 byp by-pass capacitor needed for internal pre-regula tor filtering. the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. 8 / 1 addr-a / addr-b address setting two i2c addresses available for each section by setting the address pins voltage level. see address pin characteristics table. 15/ 26 isel-a / isel-b current selection the resistors ?r sel ? connected between i sel and gnd define the linear regulators current limit protection threshold by the equation: i max(typ) = 10000 / r sel . 14 / 27 reserved reserved to be left floa ting. do not connect to gnd. table 2. pin description (continued)
maximum ratings LNBH24L 10/25 doc id 16857 rev 2 4 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to network ground terminal. table 3. absolute maximum ratings (valid for both sections a/b) symbol parameter value unit v cc-l , v cc dc power supply input voltage pins -0.3 to 16 v i out output current internally limited ma v orx dc output pin voltage -0.3 to 25 v v otx tone output pin voltage -0.3 to 25 v lx lx input voltage -0.3 to 25 v v up dc input voltage -0.3 to 24 v v i logic input voltage (ttx, sda, scl, dsqin, addr pins) -0.3 to 7 v v oh logic high output voltage (pdc pin) -0.3 to 7 v v extm extm pin voltage -0.3 to 2 v v byp internal reference pin voltage (1) 1. the byp pin is intended only to connect an external ceramic c apacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. -0.3 to 4.6 v isel current selection pin voltage -0.3 to 4.6 v t stg storage temperature range -50 to 150 c t j junction temperature range -25 to 150 c esd esd rating with human body model (hbm) for all pins unless 4, 21, 22 2 kv esd rating with human body model (hbm) for pins 21, 22 4 esd rating with human body model (hbm) for pin 4 0.6 table 4. operating ratings symbol parameter value unit v cc-l , v cc dc power supply input voltage pins 8 to 15 v t j junction temperature range 0 to 125 c table 5. thermal data symbol parameter value unit r thjc thermal resistance junction-case 2 c/w r thja thermal resistance junction-ambient with device soldered on 2s2p pc board 35 c/w
LNBH24L application circuits doc id 16857 rev 2 11/25 5 application circuits figure 3. LNBH24L with internal tone for diseqc 1.x applications d3 l1 v in 12v to lnb 500ma max pdc lx vup vorx extm c1 LNBH24L (sections a/b) p-gnd a -gnd d1 c10 220nf vcc-l vcc c8 220nf votx isel r2 (rsel) 15kohm byp c11 220nf extm c15 47 nf r9 2kohm d3 d3 l1 v in 12v to lnb 500ma max d2 d2 d2 pdc lx vup vorx extm c1 p-gnd a -gnd p-gnd a -gnd d1 d1 c10 220nf c10 220nf vcc-l vcc c8 220nf vcc-l vcc c8 220nf c8 220nf c15 47 nf r9 r9 c6 2.2f c6 c3 c3 c3 i 2 c bus scl addr ttx { sda dsqin tone enable control ttl d4 d3 l1 v in 12v to lnb 500ma max pdc lx vup vorx extm c1 LNBH24L (sections a/b) p-gnd a -gnd d1 c10 220nf vcc-l vcc c8 220nf votx isel r2 (rsel) 15kohm byp c11 220nf extm c15 47 nf r9 2kohm d3 d3 l1 v in 12v to lnb 500ma max d2 d2 d2 d2 d2 d2 pdc lx vup vorx extm c1 p-gnd a -gnd p-gnd a -gnd d1 d1 c10 220nf c10 220nf vcc-l vcc c8 220nf vcc-l vcc c8 220nf c8 220nf c15 47 nf r9 r9 c6 2.2f c6 c3 c3 c3 c6 2.2f c6 c3 c3 c3 c3 c3 c3 i 2 c bus scl addr ttx { sda i 2 c bus scl addr ttx { sda dsqin tone enable control ttl dsqin tone enable control ttl d4 d4 figure 4. diseqc 1.x using external 22 khz tone generator source through extm pin l1 vin 12v to lnb 500ma max d2 lx vup vorx c1 p-gnd a-gnd d1 c10 220nf votx i 2 c bus scl extm addr ttx c15 220nf 22 khz signal source { sda pdc isel r2 (rsel) 15kohm byp c11 220nf dsqin vcc c8 220nf d3 - c bus c8 220nf vcc- l LNBH24L (sections a/b) c6 2.2f c3 -- - l1 vin 12v to lnb 500ma max d2 lx vup vorx c1 p-gnd a-gnd d1 c10 220nf votx i 2 c bus scl extm addr ttx c15 220nf 22 khz signal source { sda pdc isel r2 (rsel) 15kohm byp c11 220nf dsqin vcc c8 220nf d3 - c bus c8 220nf vcc- l LNBH24L (sections a/b) c6 2.2f c3 -- -
application circuits LNBH24L 12/25 doc id 16857 rev 2 equation 2 figure 5. LNBH24L with pdc circuit for diseqc 1.x applications d3 l1 v in 12v to lnb 500ma max d2 pdc lx vup vorx extm c1 p-gnd a -gnd d1 c10 220nf vcc-l vcc c8 220nf votx isel r2 (rsel) 15kohm byp c11 220nf d8 1n4148 *r7 22 ohm *c14 1nf *r5 2.2k ohm 3.3v *tr1 c15 47 nf r9 2kohm *r8 150 ohm d3 d3 l1 v in 12v to lnb 500ma max d2 d2 pdc lx vup vorx extm c1 p-gnd a -gnd p-gnd a -gnd d1 d1 c10 220nf c10 220nf vcc-l vcc c8 220nf vcc-l vcc c8 220nf c8 220nf votx isel r2 (rsel) 15kohm byp c11 220nf isel r2 (rsel) 15kohm r2 (rsel) 15kohm byp c11 220nf byp c11 220nf c11 220nf *r7 22 ohm *c14 1nf *r5 2.2k ohm 3.3v *tr1 c15 47 nf r9 r9 (*)optional components. to be used only in case of heavy capacitive load (*)optional components. to be used only in case of heavy capacitive load *r8 150 ohm LNBH24L (sections a/b) i 2 c bus scl addr ttx { sda dsqin tone enable control ttl c6 2.2f c6 c3 c3 c3 d4 d3 l1 v in 12v to lnb 500ma max d2 pdc lx vup vorx extm c1 p-gnd a -gnd d1 c10 220nf vcc-l vcc c8 220nf votx isel r2 (rsel) 15kohm byp c11 220nf d8 1n4148 *r7 22 ohm *c14 1nf *r5 2.2k ohm 3.3v *tr1 c15 47 nf r9 2kohm *r8 150 ohm d3 d3 l1 v in 12v to lnb 500ma max d2 d2 pdc lx vup vorx extm c1 p-gnd a -gnd p-gnd a -gnd d1 d1 c10 220nf c10 220nf vcc-l vcc c8 220nf vcc-l vcc c8 220nf c8 220nf votx isel r2 (rsel) 15kohm byp c11 220nf isel r2 (rsel) 15kohm r2 (rsel) 15kohm byp c11 220nf byp c11 220nf c11 220nf *r7 22 ohm *c14 1nf *r5 2.2k ohm 3.3v *tr1 c15 47 nf r9 r9 (*)optional components. to be used only in case of heavy capacitive load (*)optional components. to be used only in case of heavy capacitive load (*)optional components. to be used only in case of heavy capacitive load (*)optional components. to be used only in case of heavy capacitive load *r8 150 ohm LNBH24L (sections a/b) i 2 c bus scl addr ttx { sda i 2 c bus scl addr ttx { sda dsqin tone enable control ttl dsqin tone enable control ttl c6 2.2f c6 c3 c3 c3 c6 2.2f c6 c3 c3 c3 c3 c3 c3 d4 d4 table 6. bill of material (valid for a and b sections unless for c1, c2, c7, c8 and c11) component notes r2, r9, r5 (1) 1/16 w resistors. refer to the typical application circuit for the relative values r7 (1) , r8 (1) 1/2 w resistors. refer to the typical application circuit for the relative values c1 25 v electrolytic capacitor, 100 f or higher is suitable c3 25 v, 220 f electrolytic capacitor, esr in the 100 m to 350 m range c6, c8, c10, c11, c15, c14 (1) 25 v ceramic capacitors. refer to the typ. appl. circuit for the relative values d1 stps130a or similar schottky diode with v rrm > 25 v and i f (av) higher than: i f(av) > i out_max x (v up_max / v in_min ) d2 stps130a, 1n5818 or similar schottky diode with vrrm>25v. to be placed as close as possible to vorx pin d3 1n4001-07 or any similar general purpose rectifier d4 bat54, stps130a, bat43, 1n5818, or similar schottky diode with vrrm>20v. to be placed as close as possible to extm pin d8 1n4148 or similar tr1 (1) bc817 or similar npn general-purpose transistor l1 22 h inductor with i sat > i peak where i peak is the boost converter peak current: (see equation 2 ) 1. these components can be added to avoid any 22 khz tone di stortion due to heavy capacitive output loads. if not needed they can be removed leav ing the pdc pin floating.
LNBH24L i2c bus interface doc id 16857 rev 2 13/25 6 i2c bus interface data transmission from main microprocessor to the LNBH24L and vice versa takes place through the 2 wires i2c bus interface, consisting of the 2 lines sda and scl (pull-up resistors to positive supply voltage must be externally connected). 6.1 data validity as shown in figure 6 , the data on the sda line must be stable during the high semi-period of the clock. the high and low state of th e data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown in figure 7 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the master (microprocessor) puts a resist ive high level on the sda line during the acknowledge clock pulse (see figure 8 ). the peripheral (LNBH24L) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the sda line remain at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. the LNBH24L won't generate acknowledge if the v cc supply is below the under-voltage lockout threshold (6.7 v typ.). 6.5 transmission without acknowledge avoiding to detect the acknowledges of the LNBH24L, the microprocessor can use a simpler transmission: simply it waits one clock withou t checking the slave acknowledging, and sends the new data. this approach of course is le ss protected from misworking and decreases the noise immunity.
i2c bus interface LNBH24L 14/25 doc id 16857 rev 2 figure 6. data validity on the i2c bus figure 7. timing diagram of i2c bus figure 8. acknowledge on the i2c bus
LNBH24L lnbh24 software description doc id 16857 rev 2 15/25 7 lnbh24 software description the LNBH24L i2c interface controls both the ic sections a and b depending on the address sent before the data byte. all the below description is valid for both sections. 7.1 interface protocol the interface protocol comprises: a start condition (s) a chip address byte [the lsb bit determines read (=1)/write (=0) transmission] a sequence of data (1 byte + acknowledge) a stop condition (p) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, two addresses for each section selectable by addr-a/b pins (see ta b l e 1 1 ) 7.2 system register (sr, 1 byte for each section a and b) write = control bits functions in write mode read = diagnostic bits in read mode. all bits reset to 0 at power on 7.3 transmitted data (i2c bus wr ite mode) for each sections a/b when the r/w bit in the section address is se t to 0, the main microprocessor can write on the system register (sr) of t he relative section (a or b, depending on th e 7 bit address value) via i2c bus. all and 8 bits are available and can be written by the microprocessor to control the device functions as per the below truth table ( ta bl e 7 ). section address (a or b) data msb lsb msb lsb s 0 0 0 1 0 x x r/w ack ack p mode msb lsb write pcl ttx ten llc vsel en test4 test5 read test1 test2 test3 llc vsel en otf olf
lnbh24 software description LNBH24L 16/25 doc id 16857 rev 2 x = don't care values are typical unle ss otherwise specified valid with ttx pin floating 7.4 diagnostic received data (i 2c read mode) for both sections a/b the LNBH24L can provide to the mcu master a copy of the diagnostic system register information via i2c bus in read mode. the read mode is master activated by sending the chip address with r/w bit set to 1. at the following master generated clocks bits, LNBH24L issues a byte on the sda data bus line (msb tr ansmitted first). at the ninth clock bit the master can: acknowledge the reception, starting in this way the transmission of another byte from the LNBH24L no acknowledge, stopping the read mode communication three bits of the register are read back as a copy of the corresponding write output voltage register status (llc, vsel, en), two bits co nvey diagnostic inform ation about the over- temperature (otf), output over-load (olf) and three bit are for internal usage (test1-2-3) and must be disregarded by the mcu software. in normal operation the diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to one. at start-up all the bits are reset to zero. table 7. truth table pcl ttx ten llc vsel en test4 test5 function 000100v orx = 13.3 v, v up =14.4 v, (v up -v orx =1.1 v typ.) 001100v orx = 18.2 v, v up =19.3 v, (v up -v orx =1.1 v typ.) 010100v orx = 14.3 v, v up =15.4 v, (v up -v orx =1.1 v typ.) 011100v orx = 19.2 v, v up =20.3 v, (v up -v orx =1.1 v typ.) 10 10 0 internal 22 khz controlled by dsqin pin (only if ttx=1) 11 10 0 internal 22 khz tone output on v otx is always activated 00 10 0 internal 22 khz generator disabled, extm modulation enabled 0100 v orx output is on, v otx tone generator output is off 1100 v orx output is on, v otx tone generator output is on 0 1 0 0 pulsed (dynamic) current limiting is selected 1 1 0 0 static current limiting is selected x x x x x 0 x x power block disabled
LNBH24L lnbh24 software description doc id 16857 rev 2 17/25 x = don?t care note: values are typical unless otherwise specified. 7.5 power-on i2c interface reset the i2c interface built in the LNBH24L is automatically reset at power-on. as long as the v cc stays below the undervoltage lockout (uvl ) threshold (6.7 v), the interface will not respond to any i2c command and the system registers (sr) are initialized to all zeroes, thus keeping the power blocks disabled. once the v cc rises above 7.3 v typ. the i2c interface becomes operative and the srs can be configured by the main microprocessor. this is due to 500 mv of hysteresis provided in the uvl threshold to avoid false re-triggering of the power-on reset circuit. 7.6 address pins for each section of the LNBH24L it is possib le to select two i2c interface addresses by means of the relevant addr pin. the addr pins are ttl compatible and can be set as per hereafter address pins characteristics see ta b l e 1 1 . 7.7 diseqc? implementati on for each section a/b LNBH24L helps system designer to implement diseqc 1.x protocol by allowing an easy pwk modulation of the 22 khz carrier through the extm and v otx pins. full compliance of the system to the specification is thus not implied by the bare use of the LNBH24L (see diseqc 1.x operation descriptions and typical application circuits). table 8. register test1 test2 test3 llc vsel en otf olf function these bits are read exactly the same as they were left after last write operation 0t j < 135c, normal operation 1t j > 150c, power blocks disabled 0i o < i omax , normal operation 1i o > i omax , overload protection triggered xx x these bits status must be disregarded by the mcu.
electrical characteristics LNBH24L 18/25 doc id 16857 rev 2 8 electrical characteristics refer to the typical application circuits, t j from 0 to 85 c, en=1, vsel=llc=ten=pcl=test4=test5=ttx=0, r sel =15 k , dsqin=low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25c. v out = v orx pin voltage. see software description section for i2c access to the system register. table 9. electrical characteristics of each sections a/b symbol parameter test conditions min. typ. max. unit v in supply voltage i out = 500 ma, vsel = llc = 1 8 12 15 v i in supply current both sections a and b enabled i out = 0 20 30 ma both sections a and b enabled, optional pdc circuit not connected. en = ten = ttx = 1, i out = 0 50 70 en = 0 6 v out output voltage vsel = 1 i out = 500 ma llc = 0 17.3 18.2 19 v llc = 1 19.2 v out output voltage vsel = 0 i out = 500 ma llc = 0 12.6 13.3 14 llc = 1 14.3 v out line regulation v in = 8 to 15 v vsel=0 5 40 mv vsel=1 5 60 v out load regulation vsel=0 or 1, i out from 50 to 500ma 200 i max output current limiting rsel= 15 k 500 800 ma rsel= 11 k 750 1000 i sc output short circuit current vsel=0/1 800 ma t off dynamic overload protection off time pcl=0, output shorted 900 ms t on dynamic overload protection on time pcl=0, output shorted t off / 10 f tone tone frequency dsqin=high or ten=1, ttx=1 18 22 26 khz a tone tone amplitude using internal tone generator dsqin=high or ten=1, ttx=1, diseqc 1.x configuration using internal generator, c bus from 0 to 250 nf, i out from 50 to 500 ma 0.4 0.650 0.9 v pp a tone tone amplitude using internal tone generator dsqin=high or ten=1, ttx=1, diseqc 1.x configuration using internal generator, i out from 0 to 500 ma, c out from 0 to 750 nf, pdc optional circuit connected to lnb bus (1) 0.4 0.650 0.9 v pp d tone internal tone duty cycle dsqin=high or ten=1, ttx=1 (using internal generator) 40 50 60 %
LNBH24L electrical characteristics doc id 16857 rev 2 19/25 t j from 0 to 85 c, v i = 12 v. symbol parameter test conditions min. typ. max. unit t r , t f tone rise or fall time dsqin=high or ten=1, ttx=1 (using internal generator) 5 8 15 s v pdc_ol pdc pin logic low i pdc = 2 ma 0.3 v i pdc_oz pdc pin leakage current v pdc = 5 v 1 a g extm external modulation gain v out / v extm , freq. from 10 khz to 50 khz 1.8 v extm external modulation input voltage extm ac coupling (2) 400 mv pp z extm external modulation impedance 2k eff dc-dc dc-dc converter efficiency i out = 500 ma 93 % f sw dc-dc converter switching frequency 220 khz v il dsqin,ttx, pin logic low 0.8 v v ih dsqin,ttx, pin logic high 2 v i ih dsqin,ttx, pin input current v ih = 5 v 15 a i obk output backward current en = 0, v obk = 21 v -6 -15 ma t shdn thermal shut-down threshold 150 c t shdn thermal shut-down hysteresis 15 c 1. guaranteed by design, but not tested in production 2. external signal maximum voltage fo r which the extm function is guaranteed table 9. electrical characteristics of each sections a/b (continued) table 10. i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i in input current sda, scl, v i = 0.4 to 4.5 v -10 10 a v ol low level output voltage sda (open drain), i ol = 6 ma 0.6 v f max maximum clock frequency scl 400 khz
electrical characteristics LNBH24L 20/25 doc id 16857 rev 2 t j from 0 to 85 c, v i = 12 v. table 11. address pins characteristics symbol parameter test condition min. typ. max. unit section ?a ? address selection v addr-a1 ?0001000(r/w)? address pin voltage range for section a r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 00.8v v addr-a2 ?0001001(r/w)? address pin voltage range for section a r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 25v section ?b ? address selection v addr-b1 ?0001010(r/w)? address pin voltage range for section b r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 00.8v v addr-b2 ?0001011(r/w)? address pin voltage range for section b r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 25v
LNBH24L package mechanical data doc id 16857 rev 2 21/25 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data LNBH24L 22/25 doc id 16857 rev 2 table 12. qfn32 (5 x 5 mm) mechanical data dim. (mm.) min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 4.85 5.00 5.15 d2 3.20 3.70 e 4.85 5.00 5.15 e2 3.20 3.70 e0.50 l 0.30 0.40 0.50 ddd 0.08 figure 9. qfn32 package dimensions 7376875/e
LNBH24L package mechanical data doc id 16857 rev 2 23/25 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 5.25 0.207 bo 5.25 0.207 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (5x5 mm.) mechanical data
revision history LNBH24L 24/25 doc id 16857 rev 2 10 revision history table 13. document revision history date revision changes 03-dec-2009 1 initial release. 18-mar-2010 2 modified: figure 3 on page 11 and figure 5 on page 12 .
LNBH24L doc id 16857 rev 2 25/25 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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